UART + FIFO Transceiver
Verilog · Icarus Verilog · GTKWave · Digital design
A synthesizable UART implementation with a synchronous FIFO buffer and self-checking testbench. I built the full TX/RX path in Verilog, simulated loopback at multiple baud settings, and verified byte-for-byte correctness before calling it done.
Overview
This project is a complete serial communication stack in hardware description language form: a configurable baud-rate generator, an 8-entry FIFO for burst writes, dedicated transmitter and receiver state machines, and a top module that ties them together. The design targets 9600 baud at a 50 MHz clock by default (CLKS_PER_BAUD = 5208) but baud rate is parameterized so it can be retargeted without rewriting the FSMs.
What I built
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baud_timer.v— Clock divider that generates a baud_tick pulse from a configurable CLKS_PER_BAUD parameter. - ·
fifo.v— 8×8 synchronous FIFO with full/empty flags so the testbench can burst-write bytes while TX drains in the background. - ·
uart_tx.v— Transmitter FSM (IDLE → START → DATA → STOP) that reads from the FIFO and shifts out serial frames. - ·
uart_rx.v— Receiver FSM with start-bit detection and baud recovery to reconstruct incoming bytes. - ·
uart_top.v— Top-level module wiring baud timer, FIFO, TX, and RX into one loopback-ready system.
How it works
UART framing: idle line is HIGH; each byte sends one start bit (LOW), eight data bits LSB-first, then one stop bit (HIGH). Both sides must agree on baud rate ahead of time.
FIFO buffering: the write interface accepts up to eight bytes in burst while the transmitter drains the queue one frame at a time, decoupling testbench/CPU timing from serial output.
Top-level flow: bytes enter through wr_en / wr_data, the TX FSM serializes them on tx, and the RX block resynchronizes on the start edge to recover rx_data with a rx_done strobe.
Verification
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uart_tx_tb.v— isolated transmitter test with a self-checking serial decoder. - ·
uart_top_tb.v— full system loopback (rx_in = tx) with automatic PASS/FAIL checks per byte. - ·Waveform debug in GTKWave via generated
uart_top.vcddumps.
Loopback test vectors exercised in simulation: